The present invention is directed to a device for transferring a signal of a desired dynamic range and precision over a link having a precision which is less than the precision of the desired signal without loosing performance of the transmitted signal. More particularly, the present invention is directed to realizing the internally gained precision of a signal processed in a digital signal processor (DSP) with a smaller amount of IO bits than is nominally required for realizing the precision and dynamic range.
Presently, analog components of receivers have been replaced with digital technology in order to reduce the number of components, to improve the product yield and to reduce the manufacturing costs. In implementing digital technology for a receiver, the required number of bits for outputting data is dictated by the desired precision of the output signal. An important part of the receiver is the filter component which reduces the bandwidth of the signal after filtering and improves the precision of the outputted signal. The improved precision of the output signal is expressed as process gain. The process gain can be calculated according to the equation: EQU PB=10*log (fbin/fbout)
where PB=the process gain in dB, fbin=the bandwidth of the input signal to the filter and fbout=the bandwidth of the output signal from the filter.
When selecting a DSP for an application, many factors are considered. In selecting a DSP, the choice of a fixed point or a floating point DSP is usually dictated by the requirements of the algorithms such as the dynamic range and accuracy. However, a compromise between various other requirements of speed, precision, program/data memory space, power consumption, cost, ease of use and available technical support for the device often leads to the selection of a particular device. Based upon these considerations, a fixed point DSP is typically used to implement the filter. In conventional and commonly used DSPs, such as TMS 320C25 and TMS 320C50 (from TI) and DSP16 (from AT & T), the number of IO bits is limited to 16 even though the number of bits internal to the DSPs is more than 16 bits.
In digital implementation, the required number of bits corresponds to the desired precision of the signal. For example, for input data with 14 bit precision and a process gain in the filter of 24 dB or four bits (where 24 dB=4 bits.times.6.02) with 6.02 being the theoretical conversion factor for an A/D converter, the precision of the internal data is 18 bits. However, in conventional DSPs having 16 IO bits, the precision and the output data is limited to the 16 IO bits and the 18 bit precision of the internal data will, therefore, not be fully realized.
One solution for realizing the full internal precision is to use a DSP with more than 16 IO bits. The disadvantages associated with using DSPs with more than 16 IO bits are increased component cost, higher bandwidth requirements on the serial IO interfaces and a reduced number of available components. Another solution to the problem of realizing the increased precision for the internal data in the DSP is to split the data into two or more words. However, when splitting the data into two or more words, a higher bandwidth is required in the serial IO interface and the DSP power required to split data is increased. Accordingly, it is desired to transfer a signal having a dynamic range and precision exceeding 16 bits over a 16 bit link without loosing performance of the signal.